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16 v rail-to-rail, zero-drift, precision instrumentation amplifier ad8230 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2004C2007 analog devices, inc. all rights reserved. features resistor programmable gain range: 10 1 to 1000 supply voltage range: 4 v to 8 v rail-to-rail input and output maintains performance over ?40c to +125c excellent ac and dc performance 110 db minimum cmr @ 60 hz, g = 10 to 1000 10 v maximum offset voltage (rti, 5 v operation) 50 nv/c maximum offset drift 20 ppm maximum gain nonlinearity applications pressure measurements temperature measurements strain measurements automotive diagnostics general description the ad8230 is a low drift, differential sampling, precision instrumentation amplifier. auto-zeroing reduces offset voltage drift to less than 50 nv/c. the ad8230 is well-suited for thermocouple and bridge transducer applications. the ad8230s high cmr of 110 db (minimum) rejects line noise in measurements where the sensor is far from the instrumentation. the 16 v rail-to-rail, common-mode input range is useful for noisy environments where ground potentials vary by several volts. low frequency noise is kept to a minimal 3 v p-p, making the ad8230 perfect for applications requiring the utmost dc precision. moreover, the ad8230 maintains its high performance over the extended industrial temperature range of ?40c to +125c. two external resistors are used to program the gain. by using matched external resistors, the gain stability of the ad8230 is much higher than instrumentation amplifiers that use a single resistor to set the gain. in addition to allowing users to program the gain between 10 1 and 1000, users can adjust the output offset voltage. connection diagram 8 7 6 5 1 2 3 4 ?v s v out r g v ref 2 ?in top view (not to scale) +v s v ref 1 +in ad8230 05063-041 figure 1. 8-lead soic (r-8) temperature (c) 150 ?50 ?30 ?10 10 30 50 70 90 110 130 offset voltage (v rti) 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 ?2.0 05063-001 figure 2. relative offset voltage vs. temperature 2 6 1 7 5 8 4 3 ad8230 v out ?5v +5 v type k thermocouple 0.1f 284? 34.8k ? 0.1f 05063-002 figure 3. thermocouple measurement the ad8230 is versatile yet simple to use. its auto-zeroing topology significantly minimizes the input and output transients typical of commutating or chopper instrumentation amplifiers. the ad8230 operates on 4 v to 8 v (+8 v to +16 v) supplies and is available in an 8-lead soic. 1 the ad8230 can be programmed for a g ain as low as 2, but the maximum input voltage is limited to approximately 750 mv.
ad8230 rev. b | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 connection diagram ....................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 thermal characteristics .............................................................. 5 esd caution .................................................................................. 5 typical performance characteristics ............................................. 6 theory of operation ...................................................................... 11 setting the gain .......................................................................... 11 level-shifting the output ......................................................... 12 source impedance and input settling time ........................... 12 input voltage range ................................................................... 13 input protection ......................................................................... 13 power supply bypassing ............................................................ 13 power supply bypassing for multiple channel systems ....... 13 layout .......................................................................................... 14 applications ................................................................................ 14 outline dimensions ....................................................................... 15 ordering guide .......................................................................... 15 revision history 9/07rev. a to rev. b changes to features and layout..................................................... 1 changes to table 1............................................................................ 3 changes to table 2............................................................................ 4 changes to layout ............................................................................ 5 inserted figure 13, figure 14, and figure 15; renumbered sequentially ....................................................................................... 7 changes to figure 16 and figure 19............................................... 8 updated outline dimensions ....................................................... 15 7/05rev. 0 to rev. a changes to excellent ac and dc performance............................1 changes to table 1.............................................................................3 changes to table 2.............................................................................4 changes to figure 7 and figure 8....................................................6 changes to figure 10 and figure 11................................................7 changes to level-shifting the output section ........................... 11 changes to figure 31...................................................................... 11 inserted figure 32 and figure 33; renumbered sequentially .. 11 changes to source impedance and input settling time section, input protection section and power supply bypassing for multiple channel systems section............................................... 12 changes to figure 36...................................................................... 13 changes to applications section.................................................. 13 10/04revision 0: initial version
ad8230 rev. b | page 3 of 16 specifications v s = 5 v, v ref = 0 v, r f = 100 k, r g = 1 k (@ t a = 25c, g = 202, r l = 10 k, unless otherwise noted). table 1. parameter conditions min typ max unit voltage offset rti offset, v osi v +in = v ?in = 0 v 10 v offset drift v +in = v ?in = 0 v, t a = ?40c to +125c 50 nv/c common-mode rejection (cmr) cmr to 60 hz with 1 k source imbalance v cm = ?5 v to +5 v 110 120 db voltage offset rti vs. supply (psr) g = 2 120 120 db g = 202 120 140 db gain g = 2(1 + r f /r g ) gain range 10 1 1000 v/v gain error 2 g = 2 0.01 0.04 % g = 10 0.01 0.04 % g = 100 0.01 0.04 % g = 1000 0.02 0.05 % gain nonlinearity 20 ppm gain drift g = 2, 10, 102 14 ppm/c g = 1002 60 ppm/c input input common-mode operating voltage range ?v s +v s v over temperature t = ?40c to +125c ?v s +v s v input differential operating voltage range 750 mv average input offset current 3 v cm = 0 v 33 300 pa average input bias current 3 v cm = 0 v 0.15 1 na output output swing ?v s + 0.1 +v s ? 0.2 v over temperature t = ?40c to +125c ?v s + 0.1 +v s ? 0.2 v short-circuit current 15 ma reference input voltage range 4 ?v s + 3.5 +v s ? 2.5 v noise voltage noise density, 1 khz, rti v in+ , v in? , v ref = 0 v 240 nv/hz voltage noise f = 0.1 hz to 10 hz 3 v p-p slew rate v in = 500 mv, g = 10 2 v/s internal sample rate 6 khz power supply operating range (dual supplies) 4 8 v operating range (single supply) 8 16 v quiescent current t = ?40c to +125c 2.7 3.5 ma temperature range specified performance ?40 +125 c 1 the ad8230 can operate as low as g = 2. however, since the diff erential input range is limited to approximately 750 mv, the ad 8230 configured at g < 10 does not make use of the full output voltage range. 2 gain drift is determined by the tc match of the external gain setting resistors. 3 differential source resistance le ss than 10 k does not result in voltage offset due to input bias current or mismatched serie s resistors. 4 for g < 10, the reference vo ltage range is limited to ?v s + 4.24 v to +v s C 2.75 v.
ad8230 rev. b | page 4 of 16 v s = 8 v, v ref = 0 v, r f = 100 k, r g = 1 k (@ t a = 25c, g = 202, r l = 10 k, unless otherwise noted). table 2. parameter conditions min typ max unit voltage offset rti offset, v osi v +in = v ?in = 0 v 20 v offset drift v +in = v ?in = 0 v, t = ?40c to +125c 50 nv/c common-mode rejection (cmr) cmr to 60 hz with 1 k source imbalance v cm = ?8 v to +8 v 110 120 db voltage offset rti vs. supply (psr) g = 2 120 120 db g = 202 120 140 db gain g = 2(1 + r f /r g ) gain range 10 1 1000 v/v gain error 2 g = 2 0.01 0.04 % g = 10 0.01 0.04 % g = 100 0.01 0.04 % g = 1000 0.02 0.05 % gain nonlinearity 20 ppm gain drift g = 2, 10, 102 14 ppm/c g=1002 60 ppm/c input input common-mode operating voltage range ?v s +v s v over temperature t = ?40c to +125c ?v s +v s v input differential operating voltage range 750 mv average input offset current 3 v cm = 0 v 33 300 pa average input bias current 3 v cm = 0 v 0.15 1 na output output swing ?v s + 0.1 +v s ? 0.2 v over temperature t = ?40c to +125c ?v s + 0.1 +v s ? 0.4 v short-circuit current 15 ma reference input voltage range 4 ?v s + 3.5 +v s ? 2.5 v noise voltage noise density, 1 khz, rti v in+ , v in? , v ref = 0 v 240 nv/hz voltage noise f = 0.1 hz to 10 hz 3 v p-p slew rate v in = 500 mv, g = 10 2 v/s internal sample rate 6 khz power supply operating range (dual supplies) 4 8 v operating range (single supply) 8 16 v quiescent current t = ?40c to +125c 3.2 4 ma temperature range specified performance ?40 +125 c 1 the ad8230 can operate as low as g = 2. however, since the diff erential input range is limited to approximately 750 mv, the ad 8230 configured at g < 10 does not make use of the full output voltage range. 2 gain drift is determined by the tc match of the external gain setting resistors. 3 differential source resistance le ss than 10 k does not result in voltage offset due to input bias current or mismatched serie s resistors. 4 for g < 10, the reference vo ltage range is limited to ?v s + 4.24 v to +v s ? 2.75v.
ad8230 rev. b | page 5 of 16 absolute maximum ratings table 3. parameter rating supply voltage 8 v, +16 v internal power dissipation 304 mw output short-circuit current 20 ma input voltage (common-mode) v s differential input voltage v s storage temperature range ?65c to +150c operational temperature range ?40c to +125c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics specification is for device in free air soic. table 4. parameter value unit ja (4-layer jedec board) 121 c/w esd caution
ad8230 rev. b | page 6 of 16 typical performance characteristics offset voltage (v rti) 9 ?9 ?3 ?6 0 3 6 samples 500 400 300 200 100 0 total number of samples = 2839 from 3 lots 05063-004 figure 4. offset voltage (rti) distribution at 5 v, cm = 0 v, t a = 25c offset voltage drift (nv/c) 50 ?50 ?30 ?10 10 30 samples 40 35 30 25 20 15 10 5 0 total number of samples = 300 from 3 lots 05063-005 figure 5. offset voltage (rti) drift distribution temperature (c) 150 ?50 ?30 ?10 10 70 30 50 110 130 90 offset voltage (v rti) 0 ?2 ?4 ?6 ?8 ?10 ?12 ?20 ?14 ?16 ?18 v s =5v v s =8v 05063-006 figure 6. offset voltage (rti) vs. temperature common-mode voltage (v) offset voltage (v rti) ?20 ?15 ?10 ?5 0 5 10 15 20 ?2 0 ?6 ?4 2 4 6 normalized for v cm = 0v 05063-007 figure 7. offset voltage (rti) vs. common-mode voltage, v s = 5 v common-mode voltage (v) offset voltage (v rti) ?20 ?15 ?10 ?5 0 5 10 15 20 ?10?8?6?4?2 0 2 4 6 8 10 normalized for v cm = 0v 05063-008 figure 8. offset voltage (rti) vs. common-mode voltage, v s = 8 v source impedance (k ? ) offset voltage (v) ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 23 01 45 6 5v supply 8v supply 05063-009 figure 9. offset voltage (rti) vs. sour ce impedance, 1 f across input pins
ad8230 rev. b | page 7 of 16 v ref (v) offset voltage (v rti) ?40 ?30 ?20 ?10 0 10 20 30 40 ?0.5 0 ?1.5 ?1.0 0.5 1.0 1.5 normalized for v ref = 0v 05063-010 figure 10. offset voltage (rti) vs. reference voltage frequency (hz) cmr (db) 60 70 80 90 100 110 120 130 10 100 1k 10k cmr with no source imbalance cmr with 1k ? source imbalance 40 50 05063-011 figure 11. common-mode rejection (cmr) vs. frequency source impedance (k ? ) cmr (db) 110 112 114 116 118 120 122 124 126 128 130 46 02 810 12 5v supply 8v supply 05063-012 figure 12. common-mode rejection (cmr) vs. source impedance, 1.1 f across input pins 10 ?10 ?1000 1000 05063-013 output voltage (mv) input common-mode voltage range (v) 8 6 4 2 0 ?2 ?4 ?6 ?8 ?800 ?600 ?400 ?200 0 200 400 600 800 ?856mv, +8.2v 0v, +8.4v +592mv, +8.2v v s = 8v ?812mv, +5v 0v, +5.5v +644mv, +5v v s = 5v ?652mv, ?5v 0v, ?5.5v +800mv, ?5v ?616mv, ?8.2v 0v, ?8.4v +840mv, ?8.2v figure 13. input common-mode voltage range vs. output voltage, g = 2 10 ?10 ?10 10 05063-014 output voltage (v) input common-mode voltage range (v) 8 6 4 2 0 ?2 ?4 ?6 ?8 ?8 ?6 ?4 ?2 0 2 4 6 8 ?7.9v, +8v v s = 8v +7.9v, +8v +4.88v, +5v v s = 5v ?4.9v, +5v +4.88v, ?5v ?4.9v, ?5v ?7.9v, ?8v +7.9v, ?8v figure 14. input common-mode voltage range vs. output voltage, g = 10 10 ?10 ?10 10 05063-015 output voltage (v) input common-mode voltage range (v) 8 6 4 2 0 ?2 ?4 ?6 ?8 ?8 ?6 ?4 ?2 0 2 4 6 8 +7.9v, +8v ?7.9v, +8v v s = 8v ?4.8v, +5.5v +4.8v, +5.5v v s = 5v ?4.8v, ?5.5v +4.8v, ?5.5v ?7.9v, ?8v +7.9v, ?8v figure 15. input common-mode voltage range vs. output voltage, g = 100
ad8230 rev. b | page 8 of 16 temperature (c) clock frequency (khz) 5.4 5.6 5.8 6.0 6.2 6.4 6.6 6.8 ?50 ?30 ?10 10 30 50 70 90 110 130 8v 5v 05063-016 figure 16. clock freq uency vs. temperature common-mode voltage (v) average input bias current (a) ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 ?2 0 ?6 ?4 2 4 6 ?40c +25c +85c 0c +125c 05063-017 figure 17. average input bias current vs. common-mode voltage, ?40c, +25c, +85c, +125c temperature (c) supply current (ma) 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 0 ?50 50 100 150 8v 5v 05063-018 figure 18. supply current vs. temperature 100 10 1k 10k 100k frequency (hz) gain (db) ?10 0 10 20 30 40 50 60 70 80 90 05063-019 figure 19. gain vs. frequency, g = 2 100 10 1k 10k 100k frequency (hz) gain (db) ?10 0 10 20 30 40 50 60 70 80 90 05063-020 figure 20. gain vs. frequency, g = 10 v out (v) nonlinearity (ppm) ?40 ?30 ?20 ?10 0 10 20 30 40 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 g = +20 05063-021 figure 21. gain nonlinearity, g = 20
ad8230 rev. b | page 9 of 16 100 10 1k 10k 100k frequency (hz) gain (db) ?10 0 10 20 30 40 50 60 70 80 90 05063-022 figure 22. gain vs. frequency, g = 100 ?10 0 10 20 30 40 50 60 70 80 90 100 10 1k 10k 100k frequency (hz) gain (db) 05063-023 figure 23. gain vs. frequency, g = 1000 source impedance (k ? ) gain error (%) ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 0.010 5 01 0 1 5 2 0 05063-024 figure 24. gain error vs. differential source impedance frequency (hz) 100k 1 10 100 1k 10k voltage noise (v/ hz) 0.35 0.30 0.20 0.25 0.15 0.10 0.05 0 05063-025 figure 25. voltage noise spectral density vs. frequency temperature ( c) positive supply current (ma) 2.50 2.70 2.90 3.10 3.30 3.50 3.70 3.90 ?50 ?30 ?10 10 30 50 70 90 110 130 2v/div 1s/div 05063-026 figure 26. 0.1 hz to 10 hz rti voltage noise, g = 100 frequency (khz) psr (db) 0 20 40 60 80 100 120 140 0.1 1 10 g = +1000 g = +10 160 g = +100 g = +2 05063-027 figure 27. positive psr vs. frequency, rti
ad8230 rev. b | page 10 of 16 frequency (khz) psr (db) 0 20 40 60 80 100 120 140 0.1 1 10 g = +100 g = +10 g = +1000 g = +2 05063-028 figure 28. negative psr vs. frequency, rti output current (ma) 12 0246810 output voltage swing (v) 10 8 6 4 2 0 ?2 ?4 ?6 ?8 ?10 ?40 c ?40 c +125 c +25 c +125 c +25 c +25 c +25 c ?40 c v s =5v v s =5v v s =8v v s =8v +125 c ?40 c +125 c 05063-029 figure 29. output voltage swing vs. output current, ?40c, +25c, +85c, +125c
ad8230 rev. b | page 11 of 16 theory of operation auto-zeroing is a dynamic offset and drift cancellation technique that reduces input-referred voltage offset to the v level and voltage offset drift to the nv/c level. a further advantage of dynamic offset cancellation is the reduction of low frequency noise, in particular the 1/f component. the ad8230 is an instrumentation amplifier that uses an auto-zeroing topology and combines it with high common- mode signal rejection. the internal signal path consists of an active differential sample-and-hold stage (preamp) followed by a differential amplifier (gain amp). both amplifiers implement auto-zeroing to minimize offset and drift. a fully differential topology increases the immunity of the signals to parasitic noise and temperature effects. amplifier gain is set by two external resistors for convenient tc matching. the signal sampling rate is controlled by an on-chip, 6 khz oscillator and logic to derive the required nonoverlapping clock phases. for simplification of the functional description, two sequential clock phases, a and b, are shown to distinguish the order of internal operation, as depicted in figure 30 and figure 31 , respectively. ? ? + + v ref c hold v ou t v +in v ?in c hold c sample r f r g preamp gain amp v diff +v cm ?v s ?v s 05063-030 figure 30. phase a of the sampling phase during phase a, the sampling capacitors are connected to the inputs. the input signals difference voltage, v diff , is stored across the sampling capacitors, c sample . because the sampling capacitors only retain the difference voltage, the common-mode voltage is rejected. during this period, the gain amplifier is not connected to the preamplifier so its output remains at the level set by the previously sampled input signal held on c hold , as shown in figure 30 . ? ? + + v ref c hold v ou t v +in v ?in c hold c sample r f r g preamp gain amp v diff +v cm ?v s ?v s 05063-031 figure 31. phase b of the sampling phase in phase b, the differential signal is transferred to the hold capacitors refreshing the value stored on c hold . the output of the preamplifier is held at a common-mode voltage determined by the reference potential, v ref . in this manner, the ad8230 is able to condition the difference signal and set the output voltage level. the gain amplifier conditions the updated signal stored on the hold capacitors, c hold . setting the gain two external resistors set the gain of the ad8230. the gain is expressed in the following equation: )2(1 g f r r gain += (1) 2 6 1 7 5 8 4 3 ad8230 v out ?v s + v s 0.1f r g r f r g v ref 1 v ref 2 0.1f 10f 10f 05063-032 figure 32. gain setting table 5. gains using standard 1 resistors gain r f r g actual gain 2 0 (short) none 2 10 8.06 k 2 k 10 50 12.1 k 499 50.5 100 9.76 k 200 99.6 200 10 k 100 202 500 49.9 k 200 501 1000 100 k 200 1002 figure 32 and table 5 provide an example of some gain settings. as table 5 shows, the ad8230 accepts a wide range of resistor values. because the instrumentation amplifier has finite driving capability, ensure that the output load in parallel with the sum of the gain setting resistors is greater than 2 k. r l ||( r f + r g ) > 2 k (2) offset voltage drift at high temperature can be minimized by keeping the value of the feedback resistor, r f , small. this is due to the junction leakage current on the r g pin, pin 7. the effect of the gain setting resistor on offset voltage drift is shown in figure 33 . in addition, experience has shown that wire-wound resistors in the gain feedback loop may degrade the offset voltage performance.
ad8230 rev. b | page 12 of 16 temperature (c) 150 ?50 0 50 100 offset voltage (v rti) 0 ?1 ?2 ?3 ?4 ?5 r f = 100k ? , r g = 1k ? r f = 10k ? , r g = 100 ? 05063-033 figure 33. effect of feedback re sistor on offset voltage drift level-shifting the output a reference voltage, as shown in figure 34 , can be used to level-shift the output. the reference voltage, v r , is limited to ?v s + 3.5 v to +v s ? 2.5 v. (for g < 10, the reference voltage range is limited to ?v s + 4.24 v to +v s C 2.75 v.) otherwise, it is nominally tied to midsupply. the voltage source used to level- shift the output should have a low output impedance to avoid contributing to gain error. in addition, it should be able to source and sink current. to minimize offset voltage, the v ref pins should be connected either to the local ground or to a reference voltage source that is connected to the local ground. 2 6 1 7 5 8 4 3 ad8230 v out ?v s + v s 0.1f r g r f 0.1f v r 05063-034 figure 34. level-shifting the output the output can also be level-shifted by adding a resistor, r o , as shown in figure 35 . the benefit is that the output can be level- shifted to as low as 100 mv of the negative supply rail and to as high as 200 mv of the positive supply rail, increasing unipolar output swing. this can be useful in applications, such as strain gauges, where the force is only applied in one direction. another benefit of this configuration is that a supply rail can be used for v r eliminating the need to add an additional external reference voltage. the gain changes with the inclusion of r o . the full expression is () ' r o f in og og f r' o f in og f out v r r v rr rrr v r r v rr r v ? ? ? ? ? ? ? ? ? + + =? ? ? ? ? ? ? ? ? + = 1 2 1 || 2 (3) the following steps can be taken to set the gain and level-shift the output: 1. select an r f value. table 5 shows r f values for various gains. 2. solve for r o using equation 4. level desired f r' o v rv r ? ?= (4) where: v r is a voltage source, such as a supply voltage. v desired-level is the desired output bias voltage. 3. solve for r g . 11 2 ? ? ? ? ? ? ? ? = f o o g r r gain r r (5) 2 6 1 7 5 8 4 3 ad8230 v out ?v s + v s 0.1f r g r f r o 0.1f v r ' 0 5063-035 figure 35. level-shifting the output without an additional voltage reference 2 6 1 7 5 8 4 3 ad8230 v out ?5v +5 v 0.1f 203 ? 9.76k ? 10.2k ? 0.1f +5v 0 5063-036 figure 36. an ad8230 with its output biased at ?4.8 v; g = 100; v desired-level = ?4.8 v source impedance and input settling time the input stage of the ad8230 consists of two actively driven, differential switched capacitors, as described in figure 30 and figure 31 . differential input signals are sampled on c sample such that the associated parasitic capacitances, 70 pf, are balanced between the inputs to achieve high common-mode rejection. on each sample period (approx imately 85 s), these parasitic capacitances must be recharged to the common-mode voltage by the signal source impedance (10 k maximum). if resistors and capacitors are used at the input of the ad8230, care should be taken to maintain close match to maximize cmrr.
ad8230 rev. b | page 13 of 16 input voltage range the input common-mode range of the ad8230 is rail to rail. however, the differential input voltage range is limited to approximately 750 mv. the ad8230 does not phase invert when its inputs are overdriven. input protection the input voltage is limited to within 0.6 v beyond the supply rails by the internal esd protection diodes. resistors and low leakage diodes can be used to limit excessive, external voltage and current from damaging the inputs, as shown in figure 37 . figure 39 shows an overvoltage protection circuit between the thermocouple and the ad8230. 2 6 1 7 5 8 4 3 ad8230 v out ?v s + v s 0.1f 200 ? 19.1k ? bav199 ?v s +v s 2.49k ? 2.49k ? bav199 ?v s +v s 0.1f 05063-037 figure 37. overvoltage input protection power supply bypassing a regulated dc voltage should be used to power the instrumentation amplifier. noise on the supply pins can adversely affect performance. bypass capacitors should be used to decouple the amplifier. the ad8230 has internal clocked circuitry that requires adequate supply bypassing. a 0.1 f capacitor should be placed as close to each supply pin as possible. as shown in figure 32 , a 10 f tantalum capacitor can be used further away from the part. power supply bypass ing for multiple channel systems the best way to prevent clock interference in multichannel systems is to lay out the pcb with a star node for the positive supply and a star node for the negative supply. using such a technique, crosstalk between clocks is minimized. if laying out star nodes is not feasible, use wide traces to minimize parasitic inductance and decouple frequently along the power supply traces. examples are shown in figure 38 . care and forethought go a long way in maximizing performance. 8 7 6 5 1 2 3 4 ?v s +v s ad8230 0.1f 0.1f 10f 10f ?v s +v s 8 7 6 5 1 2 3 4 ?v s +v s ad8230 0.1f 0.1f 8 7 6 5 1 2 3 4 ?v s +v s ad8230 0.1f 0.1f 8 7 6 5 1 2 3 4 ?v s +v s ad8230 0.1f 0.1f 8 7 6 5 1 2 3 4 ?v s +v s ad8230 0.1f 0.1f 1f 1f 1f 1f 8 7 6 5 1 2 3 4 ?v s +v s ad8230 0.1f 0.1f 8 7 6 5 1 2 3 4 ?v s +v s ad8230 0.1f 0.1f 8 7 6 5 1 2 3 4 ?v s +v s ad8230 0.1f 0.1f 8 7 6 5 1 2 3 4 ?v s +v s ad8230 0.1f 0.1f 10f 10f star +v s star ?v s 05063-038 figure 38. use star nodes for +v s and ?v s or use thick traces and decouple frequently along the supply lines
ad8230 rev. b | page 14 of 16 layout the ad8230 has two reference pins: v ref 1 and v ref 2. v ref 1 draws current to set the internal voltage references. in contrast, v ref 2 does not draw current. it sets the common mode of the output signal. as such, v ref 1 and v ref 2 should be star-connected to ground (or to a reference voltage). in addition, to maximize cmr, the trace between v ref 2 and the gain resistor, r g , should be kept short. applications the ad8230 can be used in thermocouple applications, as shown in figure 3 and figure 39 . figure 39 is an example of such a circuit for use in an industrial environment. series resistors and low leakage diodes serve to clamp overload voltages (see the input protection section for more information). 2 6 1 7 5 8 4 3 ad8230 v out ?v s + v s 0.1f 200 ? 19.1k ? type j thermocouple ?v s +v s 1f bav199 ?v s +v s 4.99k ? 4.99k ? 100m ? 100m ? bav199 ?v s +v s 0.1f 0 5063-039 figure 39. type j thermocouple with overvoltage protection and rfi filter an antialiasing filter reduces unwanted high frequency signals. the matched 100 m resistors serve to provide input bias current to the input transistors and serve as an indicator as to when the thermocouple connection is broken. well-matched 1% 4.99 k resistors are used to form the antialiasing filter. it is good practice to match the source impedances to ensure high cmr. the circuit is configured for a gain of 193, which provides an overall temperature sensitivity of 10 mv/c. 2 6 1 7 5 8 4 3 ad8230 v out ?v s + v s 0.1f 1k ? 102k ? 350 ? 350 ? 350 ? 350 ? +v s ?v s 4k ? 1f 0.1f 05063-040 figure 40. bridge measurement with filtered output measuring load cells in industrial environments can be a challenge. often, the load cell is located some distance away from the instrumentation amplifier. the common-mode potential can be several volts, exceeding the common-mode input range of many 5 v auto-zero instrumentation amplifiers. fortunately, the wide common-mode input voltage range of the ad8230 spans 16 v, relieving designers of having to worry about the common-mode range.
ad8230 rev. b | page 15 of 16 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-a a 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 41. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) ordering guide model temperature range package description package option AD8230YRZ 1 ?40c to +125c 8-lead soic_n r-8 AD8230YRZ-reel 1 ?40c to +125c 8-lead soic_n, 13" tape and reel r-8 AD8230YRZ-reel7 1 ?40c to +125c 8-lead soic_n, 7" tape and reel r-8 ad8230-eval evaluation board 1 z = rohs compliant part.
ad8230 rev. b | page 16 of 16 notes ?2004C2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05063-0-9/07(b)

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